1. Field of the Invention
The present invention relates to a semiconductor device and more particularly relates to a semiconductor device in which an equalizing circuit is provided in a sense amplifier.
2. Description of Related Art
As generally known, data stored in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is read by amplifying a potential difference appeared at a pair of bit lines through read operation. To perform sense operation, it is necessary to precharge the pair of bit lines to the same potential and, in general, a bit line driven to high potential (VARY) and a bit line driven to low potential (VSS) are short-circuited using an equalizing circuit to perform the precharge operation. In this case, the precharge level is set to intermediate potential (VBLP) between the VARY and VSS.
In recent years, the internal voltage of a semiconductor device is lowered for reduction of power consumption. Thus, when a pair of bit lines are short-circuited using an equalizing circuit, the gate-source and gate-drain voltages of a transistor constituting the equalizing circuit become small, resulting in much time being required in the equalizing operation. For example, assuming that the internal potential VPERI is 1.0 V and precharge level VBLP is 0.5 V, the gate-source voltage (VPERI-VBLP) of a transistor constituting the equalizing circuit is 0.5 V. That is, it is difficult to ensure sufficient ON-current.
In order to solve the above problem, there can be considered a method of driving the transistor constituting the equalizing circuit with higher potential as disclosed in Japanese Patent Application Laid-Open No. 2003-132679.
However, in a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2003-132679, a boost potential is used as an equalizing signal is generated. Using the boost potential poses a problem in increases in not only circuit scale but also power consumption. In order to suppress these increases, there is a method of directly using an external potential VDD as the equalizing signal is generated. In this case, however, the timing of the equalizing signal is changed depending on the voltage condition of the external potential VDD. As a result, it becomes difficult to adjust a timing between a signal to control a word line, which is controlled by internal potential and thus relatively less influenced by the voltage condition of the external potential VDD, and a equalizing signal. In some cases, equalizing operation may erroneously start before reset of the word line.